Conventional layouts and device structures for manufacturing a trench semiconductor power device integrated with Gate-Source ESD clamp diodes for providing an ESD protection still have a limitation. A prior art U.S. Pat. Pub. No. 2008/0290367 discloses several kinds of structures that comprise a trench semiconductor power device integrated with ESD clamp diodes. FIG. 1A is a top view of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 100 which includes a gate metal pad 102 connected to a gate metal runner 103 disposed on the peripheral edges of the device 100 and a source metal pad 101. There is a metal gap 104 opened between the source metal pad 101 and the gate metal pad 102 and the gate metal runner 103. Gate-Source ESD clamp diodes 105 are connected between the gate metal runner 103 and the source metal pad 101. FIG. 1B is a top view of another MOSFET device 110 that includes a gate metal pad 112 connected to gate metal runners 113 and a source metal pad 111 with a metal gap 114 disposed between them. Unlike the MOSFET device 100 in FIG. 1A, the MOSFET 110 in FIG. 1B further comprises poly-silicon resistors 115 together with Gate-Source ESD clamp diodes 116 which are connected between the gate metal runner 113 and the source metal pad 111. And furthermore, in FIG. 1B, there is another kind of Gate-Source ESD clamp diode 117 which is connected between the gate metal pad 112 and the source metal pad 111. All the Gate-Source ESD clamp diodes in FIG. 1A and FIG. 1B comprise multiple back to back Zener diodes with alternating n+ doped regions next to p+ doped regions, wherein the alternating n+ doped regions and p+ doped regions have a stripe structure which would have a leakage path along an edge of the Gate-Source ESD clamp diodes because the dry poly-silicon etch step in the manufacturing process would damage the edge of the Gate-Source ESD clamp diodes.
FIG. 1C is a cross-section view of a MOSFET device integrated with Gate-Source ESD clamp diodes disclosed in the prior art discussed above, which shows that an Gate-Source ESD clamp diode is connected between a gate metal pad 121 and a source metal pad 122, wherein the gate metal pad 121 is further connected to a first type trenched gate 125 encompassed in a body region 123 for gate connection, and the source metal pad 122 is further connected to source regions 124 flanking second type trenched gates 126 in the body regions 123. The body regions 123 are formed only underneath the edges of the Gate-Source ESD clamp diode, which would cause early breakdown occurrence at corners of the body regions 123.
Therefore, there are only two types of Gate-Source ESD clamp diodes in the prior art: a first type is formed between the gate metal pad and the source metal pad, and a second type is formed between the source metal pad and the gate metal runner. Especially for small-size devices, there is not much space budget for the Gate-Source ESD clamp diodes due to the size limitation of dies, which requires increasing the total perimeter of the Gate-Source ESD clamp diodes for ESD capability enhancement.
Therefore, there is still a need in the art of the semiconductor power device integrated with Gate-Source ESD clamp diodes, to provide a novel cell structure, device configuration and layout that would further increase total perimeter of the Gate-Source ESD clamp diodes for ESD capability enhancement without sacrificing other performances and improve other characteristics of the semiconductor power device.